1. Field of the Invention
The present invention relates to a method for reducing a reset current for resetting a portion of a phase change material in a memory cell of a phase change memory device and a phase change memory device.
2. Description of the Related Art
FIG. 1 illustrates a prior art structure of a phase change memory cell. As shown, a lower insulating layer 102 is formed over a substrate 100. A first contact hole 105 is formed in the lower insulating layer 102, and a lower electrode 113 (sometimes referred to as a heater) is formed in the first contact hole 105. Typically, the lower electrode 113 is formed of TiAlN, TiN, etc. A phase change material 115 is formed on the lower insulating layer 102 over the lower electrode 113. Typically, the phase change material is a chalcogenide material such as Ge2Sb2Te5, etc. An upper electrode 119 is formed on the phase change material 115. The upper electrode 119 may be formed from TiN, TaN, WN, etc. An upper insulating layer 122 is formed over the substrate 100. A second contact hole 125 is formed in the upper insulating layer 122 to expose a portion of the upper electrode 119. A conductive plug 127 is formed in the second contact hole 125. The conductive plug 127 may be formed of W, Al, Cu, etc. A metal pattern 129 (e.g., conductive line) may then be formed over the upper insulating layer 122 in contact with the plug 127. The metal pattern may be formed of the same material as the plug 127. Typically, the metal pattern 129 is a bitline of the phase change memory device including the phase change memory cell of FIG. 1.
The memory cell of FIG. 1 is programmable based on the application of heat to the phase change material 115. The application of heat may be performed by passing a current through the phase change material 115 (e.g., by applying current to the upper electrode 119). FIG. 2A illustrates both the current reset pulse and current set pulse for programming the phase change material 115. As shown in FIG. 2A, the reset pulse is a high current supplied for short period of time, while the set pulse is a lower current for a longer period of time. As shown in FIG. 2B, the reset pulse has the effect of increasing the resistance of the phase change material 115, while the set pulse has the effect of lowering the resistance of the phase change material 115. The change in resistance is brought about by a change in the state of the phase change material 115. The reset pulse causes a programmable volume of the phase change material 115, such as shown in FIG. 3, to become amorphous. By contrast, the set pulse causes the programmable volume of the phase material 115 to become crystalline. The higher resistance amorphous state generally corresponds to the storage of a logic “one,” while the lower resistance crystalline state corresponds to the storage of a logic “zero”.
To maintain low power consumption, it is desirable for both the reset current and the set current to be relatively low. However, it is also desirable that the resulting resistance of the phase change material as a result of the reset operation have as large a difference as possible with respect to the resistance of the phase change material after the set operation. Generally, as the reset current is reduced, the difference in resistivity between the reset and set states diminishes. Thus, an unfavorable tradeoff exists between trying to achieve low set and reset currents, while also maintaining a desirable difference in the set and reset resistances.